The present invention relates to computer systems and more particularly to limiting the power consumed in an integrated circuit by throttling the frequency or controlling a pipeline of the integrated circuit in response to a high power condition.
Computer systems, from small handheld electronic devices to medium-sized mobile and desktop systems to large servers and workstations, are becoming increasingly pervasive in our society. Computer systems typically include one or more processors. A processor manipulates and controls the flow of data in a computer by executing instructions. To provide more powerful computer systems for consumers, processor designers strive to continually increase the operating speed of the processor. Unfortunately, as processor speed increases, the power consumed by the processor tends to increase as well. Historically, the power consumed by the processor has been limited by two factors. First, as power consumption increases, the processor tends to run hotter, leading to thermal dissipation problems. Second, as power consumption increases, the battery life of mobile computer systems decreases, leading to less attractive systems for consumers.
Processor and computer system designers have developed numerous methods to deal with these issues. For example, processor designers implement specialized circuit design techniques that reduce power consumption. In addition, modern computer systems are designed to shut down portions of the system that are not needed during a particular period of time. Both of these techniques conserve power and help extend battery life.
To address the thermal issue, elaborate thermal dissipation systems are often affixed to the processor to help dissipate the heat from the processor to the ambient environment. Some processor packages include a thermal sensor to monitor the temperature of the processor. If the processor temperature exceeds a particular threshold, the processor is placed into low power mode until it cools off. If these precautions are not taken, the processor may destroy itself by its own heat.
A method and apparatus are described for managing the power consumed in an integrated circuit (IC). In accordance with one embodiment of the present invention, a portion of an IC is operated at a high operating frequency while the IC communicates at a bus frequency during a first period of time. A throttle signal is sent to the IC, and in response, the high operating frequency is reduced to a low operating frequency. The portion of the IC is then operated at the low operating frequency while the IC communicates at the bus frequency during a second period of time. In accordance with another embodiment of the present invention, the IC, while potentially continuing to operate at a high operating frequency, stalls at least a portion of a pipeline or issues no-ops to the pipeline in response to the throttle signal.